Recently, a synchronous DRAM to synchronize with a 200 MHz or higher frequency external clock has been developed with an increase in operation speed of DRAMS. In such a synchronous DRAM, severer than those of the conventional DRAMs standards as to setup time and hold time characteristics of a command signal etc. relating to synchronous operation will be required.
Japanese patent application laid-open No.9-13587 (1997), which is filed by the assignee of this application, has proposed a semiconductor memory device (hereinafter referred to as first conventional semiconductor memory device'). In the first conventional semiconductor memory device, an external clock CLK, external command control signals such as external clock enable CKE, chip select CSB, row address strobe RASB, column address strobe CASB and write enable WEB, and addresses A0 to Ai are supplied. Also, data DQ0 to DQj as data signals are supplied to a data input and output terminal. Here, `B` attached to the respective signal names means a Low level enable signal to activate at Low level. In write and read operations, by using a rising edge of external clock CLK as a reference, the inputting of the address and various command control signals and the inputting and outputting of data are conducted.
Referring to FIG. 1, the first conventional semiconductor memory device is composed of an internal clock generating circuit 1 that generates an internal clock ICLK for the operation timing control within the memory device in response to an external clock CLK supplied, input buffers 12 to 16 that buffer and amplify the respective command control signals CKE, CSB, RASB, CASB and WEB and output corresponding internal signals S12 to S16, register circuits 121 to 124 that latch and hold the respective internal signals S13 to S16 corresponding to the command control signals CSB, RASB, CASB and WEB and output corresponding latch signals S21 to S24, command decoding circuits 31, 32, . . . that decode the command control signals in response to the latch signals S21 to S24 supplied and output command decode signals S31, S32, . . . , and D-type latch circuits 41, 42, . . . that latch the command decode signals S31, S32, . . . and output corresponding operation mode judgement signals MODE1, MODE2, . . . .
The internal clock generating circuit 1 is composed of an input buffer 11 that buffers and amplifies the external clock CLK and outputs a corresponding internal clock S11, and an internal clock activating circuit 2 that is activated in response to signal S12 supplied and generates the internal clock ICLK while synchronizing with the internal clock S11.
Referring to FIGS. 1 and 2, the operation of the first conventional semiconductor memory device will be explained below. FIG. 2 is a time chart showing the operation waveforms of the respective signals.
First, the input buffer 11 receives the external clock CLK, and then outputs in-phase clock S11 with CMOS level according to Low level/High level of CLK, regardless of the level of the external clock enable signal CKE. The internal clock activating circuit 2 is activated in response to High level of the output signal S12 of the input buffer 12 supplied with CKE, receiving clock S11, then outputting the internal clock ICLK to synchronize with clock S11 to the internal circuit.
The input buffers 13 to 16 receive the respective command control signals CSB, RASB, CASB and WEB and then output the corresponding internal signals S13 to S16. The register circuits 121 to 124 latch and hold the internal signals S13 to S16 while synchronizing with the rising edge of the internal clock S11 corresponding to the external clock, and then output the internal signals S21 to S24 to the command decoding circuits 31, 32, . . . . The command decoding circuits 31, 32, . . . output the command decode signals S31, S32, . . . that correspond to the combinations of level states of the internal signals S21 to S24 to the latch circuits 41, 42, . . . . The latch circuits 41, 42, . . . latch the command decode signals S31, S32, . . . while synchronizing with the internal clock ICLK, and then output the corresponding operation mode judgement signals MODE1, MODE2, . . . .
Though the final judgement of operation mode in the command decode circuits 31, 32, . . . actually uses the address signals, their explanations are omitted herein, as a matter of convenience for explanation. Also, in fact, between Low level and High level of the external signal, the propagation delays from input pads to the latch circuits are not equal, but they are treated as equal, as a matter of convenience for explanation.
Referring to FIG. 2, particularly, the operation timing will be detailed below. With High level of the external clock enable signal CKE, the external clock CLK becomes effective. Also, the respective external command control signals CSB, RASB, CASB, WEB etc. are input having an external setup time tSe and an external hold time the to the external clock CLK. Thus, signals S13 to S16 are varied delaying by a buffer delay Ta, i.e., a delay in passing through the input buffers 13 to 16 and a delay raised by wiring etc., to each of the external command control signals CSB, RASB, CASB and WEB. Then, signals S13 to S16 are latched and held by the register circuits 121 to 124 while synchronizing with the rising edge of the internal clock S11.
Then, the command decode signals S31, S32, . . . are varied delaying by a decode time T1, i.e., a delay in passing through the command decoding circuits 31, 32, . . . and a delay caused by wiring etc. Then, the latch circuits 41, 42, . . . , as described earlier, latch these command decode signals S31, S32, . . . while synchronizing with the internal clock ICLK and output the operation mode judgement signals MODE1, MODE2, . . . .
Thus, the reason why the latch circuits 41, 42, . . . are provided is to prevent an interference, such as noise and hazard, to the operation mode judgement signals.
Now, considered is a mode judgement time Tout from the inputting an internal window width tWi as the sum of an internal setup time tSi and an internal hold time tHi of chip and the external clock CLK until the outputting of the operation mode signal. This mode judgement time Tout affects an access time.
First, referring to FIGS. 1, 2 and 3A that shows, specifically as a matter of convenience for explanation, the details of the register circuit 121, command decoding circuit 31 and D-type latch circuit 41, the mode judgement operation of the first conventional semiconductor memory device will be detailed below.
The register circuit 121 is composed of master and slave D-type latches 21, 22 that include transfer gates SW1, SW2, respectively composed of PMOS and NMOS transistors. The latch 41 is a D-type latch that includes a transfer gate SW3.
Also, as a matter of convenience for explanation, the internal setup time tSi and the internal hold time tHi are defined as follows: Namely, the internal setup time tSi is a time from the determining the level of an input signal S13B' to the slave D-type latch 22 until the opening of the transfer gate SW2. On the other hand, the internal hold time tHi is a time from the closing of the transfer gate SW1 of the master D-type latch 21 until the varying from a determined state of an input signal S13 on the master side.
Also, both a signal propagation time of the D-type latch and a time required to generate complementary clocks S11B, ICLKB to the clock S11 and internal clock ICLK, respectively are defined as .DELTA.t.
Referring to FIG. 2, the external setup time tSe and external hold time the, and the internal window width tWi are given by the following expressions, where the internal window width tWi is 2* .DELTA.t smaller than an external window width tWe. EQU tSe+tHe=.DELTA.t+tSi+.DELTA.t+tHi [1] EQU tWi=tWe-2*.DELTA.t [2]
On the other hand, the mode judgement time Tout is given by the following expression, where T2 represents a delay time from the external clock CLK to the internal clock ICLK. EQU Tout=T2+.DELTA.t [3]
Namely, in low-speed operation, as to the standard of setup time and hold time, the reduction in window width can be a negligible level, compared with the window width. However, in 200 MHz or more high-frequency operation, the reduction in window width cannot be neglected.
Next, a second conventional semiconductor memory device will be explained in FIG. 4, wherein like parts are indicated by like reference numerals and letters as used in FIG. 1. The difference between the first conventional semiconductor memory device and the second conventional semiconductor memory device is that latch timing is synchronized with the internal clock ICLK instead of the register circuits 121 to 124, and D-type latch circuits 21 to 24 are provided having a master-slave relation with the latch circuits 41, 42, . . . on the output side.
Referring to FIGS. 4 and 5, the operation of the second conventional semiconductor memory device will be explained below. FIG. 5 is a time chart showing the operation waveforms of the respective signals.
First, like the first conventional semiconductor memory device, the input buffer 11 receives the external clock CLK, and then the internal clock activating circuit 2 is activated in response to an internal signal S12 supplied. Also, the input buffers 13 to 16 receive the respective command control signals CSB, RASB, CASB and WEB and then output the corresponding internal signals S13 to S16. The fatch circuits 21 to 24 latch and hold the internal signals S13 to S16 while synchronizing with the rising edge of the internal clock ICLK and then output the internal signals S21 to S24 to the command decoding circuits 31, 32, . . . .
In this composition, the internal hold time tHi is defined by the master latch circuits 21 to 24, and the internal hold time tSi is defined by the slave latch circuits 41, 42, . . . .
Referring to FIG. 5, particularly, the operation timing will be detailed below. Like the first conventional semiconductor memory device, with High level of the external clock enable signal CKE, the external clock CLK becomes effective. Also, the respective external command control signals CSB, RASB, CASB, WEB etc. are input with having an external setup time tSe and an external hold time tHe to the external clock CLK. Thus, signals S13 to S16 are varied delaying by a buffer delay Ta in the input buffers 13 to 16 to each of the external command control signals CSB, RASB, CASB and WEB.
Then, the command decode signals S31, S32, . . . are varied delaying by a delay .DELTA.t in passing through the master latch circuits 21 to 24 and a decode time T1 of the command decoding circuits 31, 32, . . . . Then, the slave latch circuits 41, 42, . . . latch these command decode signals S31, S32, . . . while synchronizing with the internal clock ICLK and output the operation mode judgement signals MODE1, MODE2, . . . .
Referring to FIGS. 4, 5 and 3B that shows, specifically as a matter of convenience for explanation, the details of the latch 21, command decoding circuit 31 and D-type latch circuit 41, the mode judgement operation of the second conventional semiconductor memory device will be detailed below.
The latch 21 is composed of a master D-type latch that includes a transfer gate SW1. The latch 41 is composed of a slave D-type latch that includes a transfer gate SW3. The other components are similar to those in the first conventional semiconductor memory device.
The internal setup time tSi is defined as a time from the determination of the level of an input signal S31 to the slave D-type latch until the opening of the transfer gate SW3. On the other hand, the internal hold time tHi is defined as a time from the closing of the transfer gate SW1 of the master D-type latch until the varying from a determined state of input signal S13 on the master side.
Again referring to FIG. 5, the external setup time tSe and external hold time tHe, and the internal window width tWi are given by the following expressions, where the internal window width tWi is (2*.DELTA.t+T1) smaller than the external window width tWe. EQU tSe+tHe=.DELTA.t+T1+tSi+.DELTA.t+tHi [4] EQU tWi=tWe-(2*.DELTA.t+T1) [5]
where T1 represents the decode time of the command decoding circuit 31.
On the other hand, the mode judgement time Tout is given by the following expression. EQU Tout=T2+.DELTA.t [6]
Also in this case, in low-speed operation, as to the standard of setup time and hold time, the reduction in window width can be a negligible level, compared with the window width. However, in 200 MHz or more high-frequency operation, the reduction in window width cannot be neglected.
As described above, in both the first conventional semiconductor memory device and the second conventional semiconductor memory device, the internal window width is reduced to the external window width to be determined by the standards of the external setup time and the external hold time. Thus, in 200 MHz or more high-frequency operation with a short window width, the reduction in window width cannot be neglected.